Summit Design Launches Visual Elite 3.0, Stays "One Step Ahead" On the Path to ESL Methodology
Partnership with Perfectus Technology Delivers Genie Elite, the First Verification Solution for Storage and Networking Applications
BOSTON--(BUSINESS WIRE)--June 3, 2002--
Summit Design, Inc., the pioneering innovator of high-level design
automation (HLDA) and electronic system-level (ESL) design tools and
methodologies, today introduced Visual Elite 3.0, the latest version
of the company's flagship product. Visual Elite 3.0 features:
- FASTC, a new high performance RTL `C'-based design style
- Support for SystemC 2.0, and
- An integrated flow with GIDEL's PROCSim (Israel) hardware
acceleration board.
Summit is also partnering with intellectual property (IP) provider
Perfectus Technology, Inc. (Santa Clara, Calif.) to deliver Genie
Elite, the first integrated design and verification platform for
storage and networking (SAN) applications using the emerging Fibre
Channel standard.
"Visual Elite is an important part in our RTL design flow, and now
features a mature, fully integrated ESL solution, which is essential
to our ability to handle the complexity of our next generation SAN
products," said Isaac Achler, director of R&D and ASIC development at
Antares Microsystems. "The ability to leverage Perfectus' verification
IP in our current design flow through Genie Elite, provides us with a
powerful solution for validating our cores within a fibre channel
domain, and for delivering them to our customers."
About Visual Elite 3.0
Visual Elite 3.0 is part of Summit's commitment and continuous
effort to deliver high value solutions to its worldwide customer base,
as well as to provide them with the tools and methodology to address
next generation design challenges.
RTL Verification Features
Visual Elite 3.0 includes FASTC -- a new high performance
`C'-based design style that targets RTL design to accelerate
simulation performance by an order of magnitude over conventional HDL
and `C' event-driven engines. FASTC blocks are seamlessly integrated
with other C/C++ and HDL blocks at any abstraction level and can be
automatically mapped into synthesizable HDL code.
To further improve verification performance, Visual Elite 3.0 is
now integrated with GIDEL's PROCSim board. This integration allows
users to dynamically allocate pre-verified HDL models onto a physical
hardware board to gain simulation speed, while seamlessly mixing
PROCSim models with other HDL models running on standard HDL
simulation engines.
ESL Features
Summit Design has enhanced Visual Elite 3.0 with SystemC 2.0 and a
full palette of standard hardware verification and debugging tools
that support mixed C/HDL design and verification flows. The Virtual
Prototype in Visual Elite 3.0 now supports software communication
links that can be embedded in the `C' blocks and in the generated
virtual prototype of the system. Visual Elite 3.0 now supports a new
Connectivity Table that allows users to efficiently handle large
structural architecture in a spreadsheet format.
About Genie Elite
One of the most critical tasks for customers is validating their
IP in the context of a domain-specific environment and verifying its
compliance with multiple communication standards. The partnership with
Perfectus allows Summit Design to leverage that company's expertise in
specific target markets and deliver domain-specific solutions that
address customer needs.
Genie Elite shortens the verification cycle through an innovative
combination of tools, IP, and methodology. It is ideally suited for
companies developing IC products in storage, networking, and wireless
communications. With a portfolio of pre-packaged verification IP
components including Fibre Channel reference models, packet
generators, protocol checkers, and test cases readily available "out
of the box," system designers and verification engineers simply "plug
in" the RTL to thoroughly verify their designs.
"We are focused on developing verification IP for the
telecommunications and storage markets using C/C++ as our preferred
language and the primary vehicle to offer such advanced verification
cores," said Chandru Rajan, vice president of sales and marketing at
Perfectus. "Genie Elite is a comprehensive solution and Summit is well
positioned with its C/C++ strategy and the product roadmap that can
best support our customers."
Pricing and Availability
Visual Elite 3.0 is priced from $15,000 U.S. list and is currently
in beta testing with availability in early Q3 2002. Genie Elite will
be available in Q3 2002 with the basic package starting from $45,000
U.S. list. For more information, visit www.sd.com, www.gidel.com, and
www.perfectus.com.
About Summit Design
Summit Design is a leading international supplier of software
products that address engineering challenges met during the
specification and implementation phases of complex hardware/software
systems. The company is privately held with primary investment from
Divestiture Growth Capital, a leading technology investment fund
dedicated to buying, financing, and growing information technology
divestitures. The world's top electronics companies use Summit
Design's products to increase engineering productivity, shorten time
to market, and improve product quality. Summit Design is headquartered
in Boston, Mass. with offices in Europe and Israel.
Note to editors: Summit Design, Visual Elite, Visual IP, Regent,
Virtual-CPU, HDL Score, Genie Elite are trademarks of Summit Design,
Inc. All other trademarks or registered trademarks are property of
their respective owners.
Contact:
Summit Design
Rami Rachamim, +972-9-9708703
rami@sd.com
or
VitalCom
Lou Covey, 650/637-8212 ext. 202
lou@vitalcompr.com
